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Hardware-in-the-Loop szimuláció hang-alapú lokalizációs algoritmus FPGA-n való implementálására

Weisz, Nikolett (2018) Hardware-in-the-Loop szimuláció hang-alapú lokalizációs algoritmus FPGA-n való implementálására. ['eprint_fieldopt_thesis_type_master' not defined] thesis, Szegedi Tudományegyetem.

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    Item Type: Thesis (['eprint_fieldopt_thesis_type_master' not defined])
    Subjects:01. Natural sciences > 01.02. Computer and information sciences
    Depositing User:TTIK szerkesztő
    Date Deposited:17 Jul 2020 11:09
    Last Modified:20 Jul 2020 07:30
    URI:https://diploma.bibl.u-szeged.hu/id/eprint/86633

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